1. Field of the Invention
The present invention relates to an IP (Internet Protocol) processor, and more particularly to an IP processor that is capable of reducing an increase in network load which may often arise in an IP network or ATM switches when a plurality of IP processors are provided at an edge portion of an IP network, due to frequent occurrence of address resolution protocol (ARP) or large volume data transfer in the IP network or the ATM switches to which these processors are connected.
2. Description of the Related Art
In recent years, it has been required for an IP network to transfer increasingly large volume of IP data at high speed, and several schemes have been proposed to use a large scale backbone to transfer large volume of data at high speed. Among them, the ATM network technology which permits high speed transfer of data has been widely introduced as a desirable backbone for this purpose.
In an ATM network, an IP processor is connected to an ATM switch, with a plurality of users connected to the ATM switch under its control. Thus, the IP processor receives an IP packet from a user under its control, executes IP address resolution protocol and transfers it to an IP packet network. The IP processor also receives an IP packet from the IP packet network, executes IP address resolution protocol and transfers it to the corresponding user under its control. The IP processor may also receive an IP packet from a user, execute IP address resolution protocol and transfer it to another IP processor having other users under its control.
FIG. 1 is a view showing an example of a conventional IP network.
In FIG. 1, a plurality of IP processors 1 to 4 are connected to the respective ATM switches 6 and 7, and the ATM switches 6 and 7 are in turn connected to an IP packet network 5 which is composed of routers and the like. Users 11 to 18 such as personal computers and workstations that are grouped under the control of each of the IP processors 1 to 4 are contained in the above-mentioned ATM switch 6 and 7. In the example shown, users 11, 12, users 13, 14, users 15, 16, and users 17, 18 are placed under the control of the IP processors 1, 2, 3, and 4, respectively.
Operation of the system as shown in FIG. 1 can be illustrated by considering a specific exemplary situation as follows. The IP processor 1 is connected to the ATM switch 6 located at the first floor in an office, and receives a large volume of packets from a user 12 under its control. The IP processor 1 transfers the packets, after executing address resolution protocol, through the ATM switch 6 and the IP packet network 5, to the IP processor 4 that is connected to the ATM switch 7 located at the second floor in the same office. The IP processor 4 transfers the packets, after executing address resolution protocol, to the user 18 under its control who is the destination of the packets.
In this case, however, if another user 14 connected to the ATM switch 6 at the first floor wishes to transfer an additional large volume of packets to the user 16 connected to the ATM switch 7 located at the second floor while the above-mentioned data are being transferred, local network load increases sharply at the interface portion between the IP packet network 5 and the ATM switches 6 and 7 as shown by dashed lines in FIG. 1. As a result, packet transfer capacity of the IP packet network 5 for the packets being transferred decreases sharply.
When large volume of data are simultaneously transferred locally at a specific point, the load on the ATM switch located at the edge portion of the interface to the backbone network increases sharply. In such a situation, high speed transfer of large volume of IP packets by the network as a whole becomes difficult, although ATM switches have inherently large capability for high speed transfer of data. The same problem can also arise from a required load of address resolution protocol that frequently happens in an IP network.